1. Field of the Invention
The present invention relates to a flip-chip type quad flat package (FC-QFP) and a leadframe. More particularly, the present invention relates to a flip-chip type quad flat package and a leadframe that can prevent abnormal collapse of bumps, lower the production cost and simplify the production process.
2. Description of the Related Art
The techniques for fabricating semiconductor devices are progressing at a rapid pace. With great advances in production techniques, many types of customized, multi-functional and yet compact and handy electronic products have been developed. In the semiconductor fabrication industry, leadframe is still one of the most commonly used carriers. According to the configuration of the leads in a leadframe, a quad flat package (QFP) can be divided into quad flat package with I-type leads (QFI), quad flat package with J-type leads (QFJ) and quad flat non-leaded package (QFN). The leads in the leadframe of the quad flat non-leaded package (QFN) are cut to align with the four sides of the chip package. It should be noted that quad flat packages have a shorter average trace so that signal transmission speed is faster. As a result, quad flat package has become one of the main options for fabricating a high frequency (for example, radio frequency bandwidth) chip package with a low pin count.
FIG. 1 is a side view of a conventional quad flat non-leaded package. FIG. 2 is a bottom view of the quad flat non-leaded package of FIG. 1. As shown in FIGS. 1 and 2, a conventional quad flat non-leaded package 100 mainly comprises a chip 110, a leadframe 120 and an encapsulant 130. The chip 110 has an active surface 112 and a corresponding back surface 114. Here, the active surface 112 is the surface on the chip 110 where active devices are formed. The active surface 112 of the chip 110 further comprises a plurality of exposed bonding pads 116.
The leadframe 120 comprises a plurality of leads 122 each having a top surface 122a and a bottom surface 122b. The bonding pads 116 on the chip 110 are connected to the top surface 122a of leads 122 through various bumps 140 so that the bonding pads 116 and the leads 122 are electrically connected. The encapsulant 130 encapsulates the chip 110, the bumps 140 and the top surface 122a of the leads 122 but exposes the bottom surface 122b of the leads 122 (as shown in FIG. 2).
FIG. 3 is a side view of a bump formed on the top surface of one of the leads in a conventional quad flat non-leaded package. In the conventional method of fabricating a quad flat non-leaded package, a bump 140 is typically formed on the top surface 122a at the end of each lead 122. Because the bump 140 is directly formed on the top surface 122a of the lead 122, the bump 140 may collapse due to the wetting of the solder ball during the reflow process. Ultimately, the height of the collapsed bump 140 is hard to control.
FIG. 4 is a perspective view showing another type of lead in a conventional quad flat non-leaded package. As shown in FIGS. 1 and 4, an additional solder mask 150 is formed on the top surface 122a of the leads 122 to prevent the collapse of bumps 140. The solder mask 150 has an opening 152 that exposes a portion of the top surface 122a near the end of the lead 122. It should be noted that the openings 152 formed in the solder mask 150 is used to limit the wetting area of the bumps 140. Furthermore, the solder mask 150 is not wettable. Hence, the solder material will not wet the solder mask 150 when the bumps 140 are bonded to the top surfaces 122a of the leads 122. In other words, the bumps 140 will precisely form inside the opening 152. However, the conventional process of forming a solder mask on the leads is complicated (need to pattern the solder mask to form openings) and expensive.